The present invention relates to a semiconductor device having a plurality of semiconductor chips stacked in the same package, and relates to a technique supplying a voltage generated in any of the plurality of semiconductor chips to another semiconductor chip as a power supply voltage.
The following is generally known as a relationship between two semiconductor chips.
One semiconductor chip is supplied with an external power supply voltage and has a regulator circuit outputting an internal power supply voltage stepped down therefrom (first semiconductor chip).
The other semiconductor chip is supplied with the internal power supply voltage as an operating power supply voltage (second semiconductor chip).
In this case, the first semiconductor chip operates at a high power supply voltage and can operate at a voltage of 4 to 25 V, for example. The second semiconductor chip operates at a lower power supply voltage than the first semiconductor chip and can operate at a voltage of 1.4 to 3.6 V, for example.
That is, the first semiconductor chip is a semiconductor chip having a higher maximum voltage value than the second semiconductor chip, when the two semiconductor chips are compared with each other in terms of the maximum voltage value shown in a catalog of semiconductor device products or the like.
Until now, the first and second semiconductor chips have been accommodated in different packages and the two semiconductor chips are supplied with power supply voltages via external terminals connected with the semiconductor chips.
However, there has been a problem that mounting the two packages on a circuit substrate side by side requires a considerably large mounting area.
The following conventional techniques are known for reducing the mounting area.
Japanese patent laid open No. 2005-183611 (Patent document 1) discloses a technique regarding a multi-chip type semiconductor device containing a regulator circuit, which has been provided externally so far, within a chip and mounting two chips side by side (in the same plane) within one package.
It is possible to make the mounting area, that is, the package size, smaller in accommodating two chips arranged side by side in one package than in arranging two packages side by side.
This document discloses that two chip are mounted in the same plane in one package, but does not further disclose a technique sufficient for operating the regulator circuit stably mounted in one package.
In addition, a chip stacking technique is generally considered as a mounting method for further reducing the package size.
However, a preceding technology search at this time has not been able to find a document focused on a stable operation of the regulator circuit in the case of chip stacking.
Meanwhile, the preceding technology search at this time has found Japanese patent No. 3732884 (Patent document 2) which discloses a technique regarding a circuit and a semiconductor device for stabilizing the regulator circuit operation.
However, this document discloses only a stabilization technique of a regulator circuit in one chip, and does not disclose a technique such as one for operating the regulator circuit stably among a plurality of chips and in a structure stacking the chips.